The present invention relates to a semiconductor integrated circuit device and, more particularly, to a complementary MOS integrated circuit device (called hereinafter "CMOS-IC") including N-channel and P-channel MOS transistors.
As well-known in the art, the CMOS-IC includes a parasitic thyristor therein. When carriers, electrons or holes, are produced in a quantity great enough to trigger the parasitic thyristor, the thyristor is turned ON to cause a so-called latch-up phenomenon which in turn stops the circuit operation of the CMOS-IC and often destroys the IC.
It is also well-known in the art that a noise voltage applied to a lead terminal of a CMOS-IC produces such carriers that trigger the parasitic thyristor. Various countermeasures prevent the latch-up phenomenon caused by the noise voltage (Reference is made to U.S. Pat. No. 3,955,210).
However, the carriers triggering the parasitic thyristor may be produced by not only the noise voltage, but also by the CMOS-IC itself. More specifically, each of the CMOS transistors formed in the CMOS-IC, when subjected to a switching operation produce carriers, which are released into the substrate region surrounding the transistor. If the transistor is of a small size, the amount of the produced carriers is small allowing almost all the carriers to be absorbed by the substrate region. Substantially no carrier is therefore transferred to other features. On the other hand, if the transistor has a large size and, particularly if such transistor is subjected to a switching operation at a high switching rate a great amount of carriers are produced, a part of a which is released to the substrate to be transferred as excess carriers to other transitors surrounding the carrier-producing transistor. As a result, the parasitic thyristor is turned ON to cause the latch-up phenomenon.
This presents a serious problem in a one-chip semiconductor substrate together with the CPU, ROM, and RAM areas. A clock pulse generating area consists of a large number of large-sized CMOS transistors operating at a high switching rate. This is because the carriers, generated at such a large-sized CMOS transistors in the clock pulse generating area, are released as excess carriers into the CPU, ROM and RAM areas, adversely affecting their functions.